- Initialize clock. Use internal RC oscilator. Check RCC_CR. Check stability of clocks before changing to them. HSIRDY. Enable and configure the PLL before using its output. An interrupt is issued when the PLL is ready. HSI is selected as system clock by default. 
- Configure GPIO to inputs except the led
- Enable prefetching. Clock setting and bus prescaling must be already configured. Flash prefetch buffer activated by default apparently. Check!!
- Disable peripherals. RCC_APB1ENR RCC_APB2ENR RCC_AHBENR
- Configure flash to use two wait states.
- Check the voltage detector section. Not clear if needs to be configured.
- Check reset reason. RCC_CSR
- Check if interrupts must be configured somehow. I think not. At least not more than just define them to go to some dummy function. Check that they must be 60 interrupt lines + 16 Cortex interrupts. Check that they are well defined in the code.


- RCC_CR, RCC_CFGR, RCC_CSR
- GPIOx_CRL, GPIOx_CRH

    Setup order: (Check for more necessary registers to check)

- Disable all interrupts. Register name? Check the interrupt table that is fine.
- Configure clocks. RCC_CR, RCC_CFGR, RCC_CSR?
  - Check which is the default clock. 
  - Is it using the PLL already? If yes then change to not use it. 
  - Configure the PLL to give the highest speed supported by the stm (PLL to value 9 I think). 
  - Wait until the PLL output is stable. HSIRDY? Interrupt?
  - Change to this PLL output.
  - Check which was the reset origin. This could be used latter. RCC_CSR
  - Clock ready.
- Check that the wait states for the flash is two.
- Check for the flash prefetching. It should be enabled. 
- Configure power. PWR_CR.
  - Check that we are in the normal operating condition.
  - Check for the voltage detector section.
  - Check other things in the register and in the users manual.
- Configure GPIOs all to inputs. GPIOx_CRL/H 
- Disable all Peripherals. RCC_APB1ENR RCC_APB2ENR RCC_AHBENR

     Testing program:

- Enable GPIO led pin as output, and toggle it for ever.


