Review and reconsider all design: done:
Current and voltage sensing with shunt resistors and GMR ICs: done
New stm32 pin usage to fit many analog ADC signals: done
virtual neutral: done
Download all datasheets: IR2110 and INA125, all other not checked: done
New ICs: ACS70331EE, MCP6V64-E_ST : done
Check ICs functionality (datasheet): done
Component values checking: done (op-amp gain and offset resistor values missing)
Create hierarchical sheets for each module: done
Check recommended circuitry for each module (datasheet): done
Create new IC symbols: done
Check pins (names, numbers, pintypes): done
Create schematics: done
Check schematics: done
Anotate components: done
Create Part and Web component fields: done
Set Part to manufacturer number and Web to distributor product webpage: done
Check availability, end-of-life, obsolete, find replacement, update fields:
Availability: missing
Check package sizing: done
For capacitors, check (voltajes): done
Try to select only one component for each main value (even if voltage is higher than necessary in some components): done
Assign corresponding footprints: done
Check and modify footprints to allow handsoldering: done
Start PCB: done
Set Design rules (Find all possible manufacturers and use the worse design rules from all the manufacturers combined): done
Make the biggest board size possible with the most affordable price to set a maximum size for the board using the Edge.Cuts layer: done
Don't forget the mounting holes for the boards: done
Set the global minimum design rules: done
Set common track widths and via sizes (GND, Power lines, analog signals, digital signals, high voltage low amp, high voltage high amp): done
Use net classes for these common track widths: done
Read netlist: done
New: kicad 5.1.2: it uses a new command: “Update PCB from Schematic”
Caution: when re-reading the netlist or updating from schematic kicad resets the “keep upright” property. This may affect labels that are upwards (for better user reading).
Assign all net points to net classes: done
Draw drafts testing different configurations of main modules, taking into account power supply lines, analog signals, digital signals, different grounds and the layer to use in each in such a way to avoid interference and many other problems: done
Position the biggest components, for each module first, then position components according to function and datasheet recommendations:: done
Construct schematic modules as PCB modules: done
Move them to final position: done
Connect them: done
Create big GND and power lines: done
Create GND planes, move lines to allow planes to permate more: done
Do via stitching: done
Do DRC checks: done
Add logos: done
Relocate vias to not disturb logos: done
Relocate Silkscreen reference names: done
Create division lines to clarify and present modules location: done
Add project name and board revision number: done
Check distances of external boards (in case of multiple connector external boards): done
Assemble external boards with 3d viewer to check mechanical and assembly problems visually (pay attention to connectors and big components): done
Check orientation of pins of stm32f4 in passthrough and all: done
Annotate in PCB special pins used in open-coroco from stm32f4: done
Edit Additional indication (port names) naming: done
Add polarity symbols for ports: done
Buy all strange components first: done
Generate fabrication files: done
Add missing 3D models: done
Use tolerances in the component properties (for resistors and relevant components)
Use the minimum recomended voltages for capacitors in the component properties